Commercial production of integrated circuit devices, such as memory dice, may involve fabrication of a large number of identical circuit patterns on a single semiconductor wafer or other bulk semiconductor substrate. It is a continuing goal of semiconductor manufacturers to increase the density of semiconductor devices fabricated on a given size of semiconductor substrate to achieve increased yield of semiconductor devices and enhanced performance thereof.
One method for increasing the density of semiconductor devices in a semiconductor assembly is to create vias (i.e., through-holes) that extend entirely through a semiconductor die; and specifically that extend from an active surface of the die to the opposing backside surface of the die. The vias may be filled with electrically conductive material to form through-substrate interconnects that provide electrical pathways from the active surface of the die to the backside surface of the die. The through-substrate interconnects may be electrically coupled to electrical contacts that are along the backside of the die, and that extend to circuit components external of the die. In some applications, the die may be incorporated into a three-dimensional multichip module (3-D MCM), and the circuit components external of the die may be comprised by another semiconductor die and/or by a carrier substrate.
Various methods for forming through-substrate interconnects in semiconductor substrates have been disclosed. For instance, U.S. Pat. Nos. 7,855,140, 7,626,269 and 6,943,106 describe example methods that may be utilized to form through-substrate interconnects.
Various problems may be encountered during the fabrication of through-substrate interconnects. For instance, electrically conductive posts of the through-substrate interconnects may extend above a backside surface of a semiconductor die at a processing stage, and it may be desired to planarize such posts to form a planarized surface extending across the posts and the die. However, copper within the posts may smear during the planarizing; and/or the posts may tip or break during the planarizing. It is desired to develop new methods of forming through-substrate interconnects which alleviate, prevent and/or overcome problems encountered with conventional processing. It is further desired to develop new through-substrate interconnect architectures.